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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit switchable
DESCRIPTION
BS616LV2025
* Very low operation voltage : 4.5 ~ 5.5V * Very low power consumption : Vcc = 5.0V C-grade: 40mA (Max.) operating current I -grade: 45mA (Max.) operating current 0.6uA (Typ.) CMOS standby current * High speed access time : -70 70ns (Max.) at Vcc = 5.0V -55 55ns (Max.) at Vcc = 5.0V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE1, CE2 and OE options * I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616LV2025 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 16 bits or 262,144 bytes by 8 bits selectable by CIO pin and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.6uA and maximum access time of 55ns in 5V operation. Easy memory expansion is provided by active HIGH chip enable2 (CE2), active LOW chip enable1(CE1), active LOW output enable(OE) and three-state output drivers. The BS616LV2025 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV2025 is available in DICE form and 48-pin BGA type.
PRODUCT FAMILY
PRODUCT FAMILY BS616LV2025DC BS616LV2025AC BS616LV2025DI BS616LV2025AI OPERATING TEMPERATURE +0 C to +70 C -40 C to +85 C
O O O O
Vcc RANGE 4.5V ~ 5.5V 4.5V ~ 5.5V
SPEED ( ns )
Vcc=5.0V
POWER DISSIPATION STANDBY Operating
( ICCSB1, Max ) ( ICC, Max )
PKG TYPE DICE BGA-48-0608 DICE BGA-48-0608
Vcc=5.0V
Vcc=5.0V
70 / 55 70 / 55
6uA 25uA
40mA 45mA
PIN CONFIGURATION
BLOCK DIAGRAM
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 2048 D0 16(8) Data Input Buffer 16(8) Column I/O
Address Input Buffer
20 Row Decoder
1024 Memory Array 1024 x 2048
. . . .
D15 CE1 CE2 WE OE UB LB CIO Vdd Vss
. . . .
Write Driver
16(8) Sense Amp 128(256) Column Decoder
16(8) Data Output
Buffer
14(16) Control Address Input Buffer
A16 A0 A1 A2 A3 A4 A5
(SAE)
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2025
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Revision 2.5 Jan. 2004
BSI
PIN DESCRIPTIONS
BS616LV2025
Name
A0-A16 Address Input SAE Address Input CIO x8/x16 select input
Function
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM. This address input incorporates with the above 17 address input select one of the 262,144 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH. This input selects the organization of the SRAM. 131,072 x 16-bit words configuration is selected if CIO is HIGH. 262,144 x 8-bit bytes configuration is selected if CIO is LOW.
CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input D0 - D15 Data Input/Output Ports Vcc Gnd
Lower byte and upper byte data input/output control pins. The chip is deselected when both LB and UB pins are HIGH. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
R0201-BS616LV2025
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Revision 2.5 Jan. 2004
BSI
TRUTH TABLE
MODE CE1 H Fully Standby X Output Disable L L H H H X CE2 X X X X X X L Read from SRAM ( WORD mode ) L H L H H H L L Write to SRAM ( WORD mode ) L H X L H H L Read from SRAM L ( BYTE Mode ) Write to SRAM L ( BYTE Mode ) H X L L X X A-1 H L H L X X A-1 L L X X X H L L H X X OE WE CIO LB X UB X X SAE
BS616LV2025
D0~7
D8~15
VCC Current
High-Z
High-Z
ICCSB, ICCSB1
High-Z Dout High-Z Dout Din X Din Dout
High-Z High-Z Dout Dout X Din Din High-Z
ICC
ICC
ICC
ICC
Din
X
ICC
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL V TERM T BIAS T STG PT I OUT PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 O C to +70 O C -40 C to +85 C
O O
Vcc
4.5V ~ 5.5V 4.5V ~ 5.5V
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
6 8
pF pF
1. This parameter is guaranteed and not 100% tested.
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Revision 2.5 Jan. 2004
BSI
DC ELECTRICAL CHARACTERISTICS (TA = 0oC to +70oC) PARAMETER NAME
V IL V IH I IL I LO V OL V OH I CC
BS616LV2025
PARAMETER
Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL
TEST CONDITIONS
Vcc=5.0V Vcc=5.0V
MIN. TYP.(1) MAX.
-0.5 2.2 ---2.4 --------0.8
Vcc+0.2
UNITS
V V uA uA V V mA
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIHor CE2=VILor OE = VIH, VI/O = 0V to Vcc Vcc = Max, I OL= 2mA Vcc = Min, IOH = -1mA Vcc = Max, CE1= VIL, CE2=VIH IDQ = 0mA, F = Fmax (3) Vcc = Max, CE1 = VIH or CE2=VIL IDQ = 0mA Vcc = Max, CE1Vcc-0.2V or CE20.2V, Other inputs Vcc - 0.2V or VIN0.2V
Vcc=5.0V Vcc=5.0V Vcc=5.0V
1 1 0.4 -40
I CCSB
Vcc=5.0V
--
--
1
mA
I CCSB1
Standby Current-CMOS
Vcc=5.0V
--
0.6
6
uA
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
R0201-BS616LV2025
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Revision 2.5 Jan. 2004
BSI
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
VDR
BS616LV2025
TEST CONDITIONS
CE1 Vcc - 0.2V or CE2 0.2V, VIN Vcc - 0.2V or VIN 0.2V CE1 Vcc - 0.2V or CE2 0.2V, VIN Vcc - 0.2V or VIN 0.2V
PARAMETER
Vcc for Data Retention
MIN.
1.5
TYP. (1)
--
MAX.
--
UNITS
V
ICCDR
Data Retention Current Chip Deselect to Data Retention Time
--
0.05
1.5
uA
tCDR tR
0 See Retention Waveform TRC (2)
---
---
ns ns
Operation Recovery Time
1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
Vcc
VIH
Vcc
VDR 1.5V
Vcc
t CDR
CE1 Vcc - 0.2V
tR
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
VDR 1.5V
Vcc
t CDR
tR
CE2 0.2V
CE2
VIL
VIL
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Revision 2.5 Jan. 2004
BSI
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 1V/ns 0.5Vcc
WAVEFORM
BS616LV2025
KEY TO SWITCHING WAVEFORMS
INPUTS MUST BE STEADY MAY CHANGE FROM H TO L
1928
OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
AC TEST LOADS AND WAVEFORMS
5.0V OUTPUT
100PF
INCLUDING JIG AND SCOPE
1928
5.0V OUTPUT
MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
5PF 1020
INCLUDING JIG AND SCOPE
,
1020
FIGURE 1A
THEVENIN EQUIVALENT 667
FIGURE 1B
OUTPUT
1.73V
ALL INPUT PULSES
Vcc GND
10%
90% 90%
10%
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
READ CYCLE
JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Data Hold from Address Change CYCLE TIME : 70ns MIN. TYP. MAX. CYCLE TIME : 55ns MIN. TYP. MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQV t E1LQV t E2LQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX
tRC tAA t ACS1 t ACS2 tBA tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH
70 -(CE1) (CE2) (LB,UB) ----(CE1,CE2) (LB,UB) 10 10 10 (CE1,CE2) (LB, UB) ---10
--------------
-70 70 70 35 35 ---35 35 30 --
55 -----10 10 10 ---10 ------------
-55 55 55 30 30 ---30 30 25 --
NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle . tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV2025
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Revision 2.5 Jan. 2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
BS616LV2025
t RC t
OH AA
t
D OUT
t OH
READ CYCLE2 (1,3,4)
CE2
t t
ACS2
ACS1
CE1
t
D OUT
(5) CLZ
t
(5)
CHZ
READ CYCLE3 (1,4)
ADDRESS
t RC
t
OE
AA
t
CE2
OE
t
OH
t t t t
(5) CLZ
ACS2
CE1
OLZ
ACS1
t t
OHZ CHZ
(5)
(1,5)
LB, UB
t
BE
t t
BA
BDO
D OUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
R0201-BS616LV2025
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Revision 2.5 Jan. 2004
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
WRITE CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time (CE2, CE1,WE) CYCLE TIME : 70ns MIN. TYP. MAX.
BS616LV2025
CYCLE TIME : 55ns MIN. TYP. MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX t E1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHOX
tWC tCW tAS tAW tWP tWR tBW tWHZ tDW tDH tOHZ tOW
70 70 0 70 35 0 30 -30 0 -5 (LB,UB)
-------------
-------30 --30 --
55 55 0 55 30 0 25 -25 0 -5
-------------
-------25 --25 --
Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active
NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle .
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
ADDRESS
t
WC
t
OE
(3)
WR
CE2
(5)
t CW
CE1
(5)
(11)
t
LB,UB
(5)
BW
t
WE
AW
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t t
DW
DH
D IN
R0201-BS616LV2025
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Revision 2.5 Jan. 2004
BSI
WRITE CYCLE2 (1,6)
BS616LV2025
t
WC
ADDRESS
CE2
(11)
CE1
(5)
t t
CW
BW
LB,UB
(5)
t
WE
AW
t WP
t
WR
(3)
(2)
t AS
(4,10)
t WHZ
D OUT
t OW t DW t
DH (8,9)
(7)
(8)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV2025
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Revision 2.5 Jan. 2004
BSI
ORDERING INFORMATION
BS616LV2025
Z YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE D: DICE A: BGA-48-0608
BS616LV2025 X X
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8mm)
R0201-BS616LV2025
E1
10
Revision 2.5 Jan. 2004

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